''Spin-On'' katkılama tekniğiyle BJT yapılarının gerçekleştirilmesi
The realization of BJT structures using spin-on doping technique
- Tez No: 39362
- Danışmanlar: PROF.DR. DURAN LEBLEBİCİ
- Tez Türü: Yüksek Lisans
- Konular: Elektrik ve Elektronik Mühendisliği, Electrical and Electronics Engineering
- Anahtar Kelimeler: BJT, Katkılama tekniği, Spin-on katkılama tekniği, BJT, Doping technique, Spin-on doping technique
- Yıl: 1992
- Dil: Türkçe
- Üniversite: İstanbul Teknik Üniversitesi
- Enstitü: Fen Bilimleri Enstitüsü
- Ana Bilim Dalı: Belirtilmemiş.
- Bilim Dalı: Belirtilmemiş.
- Sayfa Sayısı: Belirtilmemiş.
Özet
ÖZET Mikroelektronik laboratuarında kullanılan“spin-on”katkılama tekniğinde katkı kaynağı maddesi yaklaşık olarak sonsuz difiizyon kaynağı davranışı gösterir ve uygulanması oldukça kolaydır. Bu tez çalışmasında, İTÜ Elektrik-Elektronik Fakültesi Anabilim Dalı Mikroelektronik Laboratuvarında spin-on katkılama tekniğiyle Bipolar J_onksiyonlu Tranzistor (BJT) yapılanmn gerçeklenmesi amaçlanmıştır. Giriş bölümünde, BJT yapılanmn gerçeklenmesi hakkında kısa bilgiler verilmiştir. Prosesin, BJTnin eleman parametrelerine etkisi ikinci bölümde incelenmiştir. BJT prosesini geliştirmek üzere tasarlanan test kırmığmda bulunan yapılar ve dikkat edilmesi gereken noktalardan söz edilmiştir. Dördüncü bölümde, yapılan proses sırasında karşılaşılan sorunlar, Çözümleri ve proses adımları verilmiştir. - v
Özet (Çeviri)
THE REALIZATION OF BJT STRUCTURES USING SPIN-ON DOPING TECHNIQUE SUMMARY One of the important doping technique is“spin-on doping technique”which is also easy appliable to the wafer. The realization of the Bipolar Junction Transistor (BJT) structures using spin-on doping technique is the aim of this thesis work. Spin-on doping technique was begun to use in early seventies, with an economical reason. The normally used predeposition diffusion techniques employ a shallow diffusion of a very high dopant concentration from the gas phase as a predeposition process. This shallow layer is then redistributed into the silicon in a subsequent diffusion step, which normally includes an oxidization cycle in order to achieve the desired junction depth and sheet resistivity as well as the required oxide thickness for masking against the following diffusion process. To carry out this drive-in diffusion normally a second furnace has to be available so that for each diffusion in the manufacture of an integrated circuit two furnaces and two diffusion process are required. Therefore the production cost is unnecessarily high, apart from the fact that the crystal perfection of the silicon is influenced by the numerous heating and cooling processes [5]. For reasonable control of the predeposition process it is usually necessary to use a surface concentration which is close to the solid solubility limit of the dopant in silicon thus resulting in a large amount of diffusion induced imperfections of the silicon lattice. Surface concentrations much lower than the solid solubility limit can only be established by long diffusions after removal of the diffusion source from the surface or by oxidizing the surface and depleting the dopant concentration. Apart from that, many gaseous sources, e.g. hydrides of phosphorus, boron and arsenic, require strict safety precautions because of their poisonousness. Therefore gaseous diffusion sources have serious disadvantages and limitations leading to a large amount of diffusion steps in wafer processing and requiring fairly sophisticated equipment. To overcome some of these disadvantages numerous methods have been reported to use doped oxides as diffusion sources. The most important advantages are: better uniformity and reproducibility, flexibility in processing and in process control, easy achievement VIof a large range of surface concentrations and diffusion profiles thus reducing diffusion induced lattice defects. The electrical characteristics of bipolar junction transistors formed in monolithic integrated circuits are influenced by a number of factors, some of which are under the control of the designer. Some of these can be controlled by the process and/or the layout. Breakdown voltages, current gain and transit time are primarily influenced by the process; frequency response is influenced by the layout as well. In order to realize bipolar junction transistors, a test chip is designed. The test chip has been drawn using layout editor computer program L-EDIT with the design rules that has been determined by laboratory possibilities. The output file of the L-EDIT is in the GDS II format. The test chip contains the structures as below: * two vertical npn low signal BJTs with different geometries, Dimensions : 310jLimx250jum and 425Mmx355jum. * two lateral npn low signal BJTs with different base-widths, Dimensions : 245/zmx245jum (xB=5jum) and 245jumx270jum (xB = 10jum). * lateral pnp low signal BJT, Dimensions : 355;umx270jum. * vertical npn power BJT, Dimensions : 450jumxl370Mm. * lateral npn power BJT, Dimensions : 390Mmxl225/um. * p-channel JFET, Dimensions : 260Mmx320Mm, (channel length : 30jum). * twinstor, * van der Pauw shape for base diffusion, * van der Pauw shape for emitter diffusion, * sheet resistance monitor for base diffusions, * sheet resistance monitor for emitter diffusions, * metal line resistance monitor, * substrate contacts, vu -19. Photolithographic process 19.1 Applying PPR to the wafer. 19.2 Patterning by the metallization mask. 20. Aluminum etching. 21. Resist stripping. 22. Aluminum sintering under N2 ambient at 450 °C, 15' To provide desired results, seven processes have been applied. During these processes the problems have been solved. The last process results are very hopeful. Some results of the process are as below. * Current gain BF is 126. * Breakdown voltages are; BVCB0 = 30V BVEB0 = 7V - x-1. Wafer cleaning. 2. Thick oxide growth (7000Â). 3. Photolithographic process 3.1 Applying NPR to the wafer. 3.2 Patterning by the base diffusion mask to open first diffusion window. 4. SiOz etching. 5. Resist stripping. 6. Applying Boron spin-on dopant“borofilm-lOO”to the wafer by spinning. 7. Base predeposition step under N2 ambient at 930 °C, 30'. 8. Drive-in process under 02 with steam at 1125°C, 50'. 9. Photolithographic process 9.1 Applying NPR to the wafer. 9.2 Patterning by the emitter diffusion mask to open second diffusion window. 10. SiOz etching. 11. Resist stripping. 12. Applying phosphor spin-on dopant“phosphorosiücafüm”to the wafer by spinning. 13. Emitter predeposition step under N2 ambient at 1050 °C, 40'. 14. Drive-in process under Oz with steam at 950 °C, 60'. 15. Photolithographic process 15.1 Applying NPR to the wafer. 15.2 Patterning by the contact windows mask. 16. SiOz etching. 17. Resist stripping. 18. Aluminum evaporating IX19. Photolithographic process 19.1 Applying PPR to the wafer. 19.2 Patterning by the metallization mask. 20. Aluminum etching. 21. Resist stripping. 22. Aluminum sintering under N2 ambient at 450 °C, 15' To provide desired results, seven processes have been applied. During these processes the problems have been solved. The last process results are very hopeful. Some results of the process are as below. * Current gain BF is 126. * Breakdown voltages are; BVCB0 = 30V BVEB0 = 7V - x
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