CMOS paralel A/D çeviricide kıyıcı türü karşılaştırıcının analizi ve tasarımı
The Analysis and design of chopper type comparator in a CMOS flash A/D converter
- Tez No: 14419
- Danışmanlar: DOÇ.DR. MELİH PAZARCI
- Tez Türü: Yüksek Lisans
- Konular: Elektrik ve Elektronik Mühendisliği, Electrical and Electronics Engineering
- Anahtar Kelimeler: Analog sayısal çeviriciler, Karşılaştırıcılar, Analog digital converters, Comparators
- Yıl: 1991
- Dil: Türkçe
- Üniversite: İstanbul Teknik Üniversitesi
- Enstitü: Fen Bilimleri Enstitüsü
- Ana Bilim Dalı: Belirtilmemiş.
- Bilim Dalı: Belirtilmemiş.
- Sayfa Sayısı: Belirtilmemiş.
Özet
ÖZET Bu çalışmada CMOS paralel analog - dijital çeviricilerde yaygın olarak kullanılan kıyıcı tipi karşılaştırıcıların çalışmaları incelenmiş; elde edilen sonuçlardan yararlanılarak 20 MHz örnekleme frekansına sahip, 8 bitlik ve ± 1/3 LSB doğrulukta bir A/D çeviricide kullanılmaya uygun bir karşı laştı rıcı tasarlanmıştır. Tasarımda, analog giriş işaretinin O ile 2. 5 V arasında değiştiği varsayılmıştır. Dolayısı ile karşılaştırıcının 2.5 V/< 2 x2> 5fc 5 mV'luk gerilim farklarını algılayıp, lojik seviyelere kuvveti en direbilecek duyarlıkta olması gerekmektedir. Karşı laştırıcının yapısının incelenmesi sonucu amaçlanan hız ve duyarlığa erişmeyi zorlaştıran iki önemli hata kaynağının varlığına karar verilmiştir: a) Sıfırlama hatası: Sıfırlama periyodu sırasında, sıfırlama suresinin kısalığından dolayı karşılaştırıcının düğüm gerilimlerinin amaçlanan değerlere belli bir hata ile yaklaşmalarından kaynak lanmakta; bu hata miktarının, karşılaştırıcının duyarlığı tarafından belirlenen belli bir hata sını rından büyük olması karşılaştırıcının yanlış çalışmasına neden olmaktadır. Sıfırlama hatasının devre para metrelerine bağı mlılığı gerek analitik olarak gerekse bilgisayar kullanılarak incelenmiş, devredeki seviye öteleme kapasitesinin değerinin küçültül meşinin hatayı küçülttüğü saptanmıştır. b) Yük enjeksiyonu : Devredeki MOS anahtarların hızla kesime gitmeleri durumunda, kanallarındaki yükler düğüm noktalarındaki parazitik kapasitelere akmakta ve bu noktalarda, karşılaştırıcının çalışmasını bozabilecek miktarda gerilim değişimlerine yol açmaktadır. Yük enjeksiyonu etkisi analitik olarak incelenmiş ve anahtarları oluşturan NMOS ve PMOS tranzistorların boyutlarının uygun seçilmesi durumunda bu hatanın kuç ültülebileceği görülmüştür. 3 /um CMOS teknolojisi kullanılarak karşı laştı rıcı tasarlanmış ve Spice simulasyonları yapılmıştır. iv
Özet (Çeviri)
SUMMARY The Analysis and Design of Chopper Type Comparator in a CMOS Flash A/D Converter The increasing speed capability and decreasing cost of digital VLSI components, has allowed the use of digital techniques for signal processing. Typical applications include video bandwidth compression, radar signature analysis, transient analysis, storage of oscilloscope traces or real-time data, distorsion analysis, and high-speed multiplexed data transmission. In recent years, digital signal processing has become one of the key functions in consumer video systems; such as digital TV and image processing. A fast, low-cost 8 bit analog-to-digi tal converter with a conversion rate of more than 20 MHz is needed for such video processing systems. CMOS flash A/D converters, with their cost- effectiveness, low power consumption and VLSI logic compatibility are well suited for use in the field of digital video signal processing. The principle most widely used to realize high-speed A/D converters is that of parallel or flash conversion CFig. 1.13. Generally, an N-bit flash con verter comprises a reference resistor string, an array of 2 comparators and subsequent encoding stages. The analog input voltage is compared simultaneously with 2 equally spaced reference voltages, and the digital results of this comparison are processed by the encoding stages to obtain the binary coded output data. The resistor ladder is used to derive 2 reference levels by linearly dividing the reference voltage. The flash architecture shows the best speed performance and can easily be implemented in an integrated circuit as a repetition of single comparator blocks and a ROM encoder structure. However, this architecture requires 2 comparators to achieve N-bit resolution, which makes it difficult to achieve a high resolution while maintaining, at the same time, a large analog bandwidth, a low power dissipation, and a small die area. In a flash ADC, internal comparators must provide the voltage amplification needed to convert a small input voltage difference into digital outputlevels that correctly represent the polarity of the input difference. So, the accuracy of the converter is determined by the resolution of the comparators. Since the encoding process of the comparator outputs into N bit is faster than the comparator function, the maximum conversion rate for the ADC is limited by the response time of its comparators. Therefore, the comparator is the key element in a converter and its design and optimization is critically important. The speed and resolution of MOS comparators are typically limited by the inherent MOSFET characteristics of low transconductance and relatively large device mismatches. However, MOS technologies also offer the substantial advantages of zero-offset analog switches and high-impedance charge storage. These attributes allow for the extensive use of circuit techniques to significantly improve the speed and resolution achievable in an MOS comparator. One of the comparator types widely used in CMOS flash A/D converters is chopper type comparator (Fig. 2.1 and Fig. 2.2). It comprises a CMOS inverter, three analog switches (TGI, TG2, TG3) and a level -shift capacitor ( Cc), and ope rates basically with complementary clock signals <p and 0 (Fig. 2.3). During the first half clock cycle (autozeroing period), the reference voltage is applied by switch TGI via level shift capacitor and held on the parasitic capacitance of the inverter. Simultaneously, the output of the inverter is connected to its input via switch TG2. This causes the inverter to be biased at the middle point of its voltage transfer curve (toggle point) which is the point of highest speed and small signal gain. Thus, level shift capacitor is charged with the reference voltage to toggle point potential difference during the autozeroing period. During the second half clock cycle (sampling period), the analog input voltage is applied by TG3 as the inverter floats actively at its toggle point. The coupling capacitor Cc subtracts the value of the stored voltage on itself from the input voltage. Thus, any difference between the Input voltage and the reference voltage is amplified by the gain of the inverter stage. The amplified signal when applied to the following matched stage results in a forced digital higher or lower decision at the trailing edge of the clock pulse. This work discusses the design of a chopper type comparator which operates at a maximum sampling rate of 20 MHz. In this design, the analog input is assumed vito range from O to 2.5 V. To achieve an 8-bit dynamic range with ± 1/2 LSB resolution, the comparator must be able to resolve input differences less than 2.5 V/( 2 x2) % 5 mV. The analysis of the comparator operation has shown that there are two important sources of error which make difficult to attain the desired speed and resolution: a) Autozeroing error: Since the comparator operates at 20 MHz, a period of the clock signal is about 50 ns. The rise time and fall time of the clock waveform are assumed to be 5 ns. Thus, in the first half clock cycle, the inverter of the comparator must be autozeroed to its equilibrium point in 20 ns. But, since the autozeroing time is too short, at the end of this period the input and output nodes of the inverter approach to the equilibrium point with an error. The problem is to decrease the amount of this error below an error limit determined by the resolution of the comparator. In order to understand the effect of circuit parameters on the autozeroing error, an analysis has been performed. The relations which approximately model the behavior of the comparator during autozeroing period have been derived. Using this relations, the curves showing the autozeroing error as a function of each circuit parameter have been drawn. It is concluded that the amount of the error is greatly dependent on the value of the level shift capacitor and decreasing the value of Cc decreases the autozeroing error. A complete analysis has been performed by numerically solving the related differential equations usi ng a computer. b) Clock feedthrough: Between the autozeroing and sampling periods, there exist a transition period during which the switches TGI and TG2 turn off. An MOS transistor holds mobile charges in its channel when it is on. When the transistor turns off, some portion of the mobile charges is transferred to the storage capacitor and causes an error in the sampled voltage. The clock voltage feedthrough through the gate-drain overlap capacitance also contributes to the error. The turnoff of an MOS switch consist of two distinct phases. During the first phase, the transistor is on and a conduction channel extends from the source to the drain of the transistor. As the gate voltage falls, mobile charges exit through both the source end and the drain end. When the gate voltage reaches the threshold voltage, the conduction channel disappears, and the transistor enters the second phase of turnoff. During this phase, only the clock feedthrough through the gate-drain overlap capacitance continues to increase the V3 1error voltage. The switch-induced error voltage on a switched capacitor can be reduced by turning off the switch very slowly to allow charges to return to the source end. But, since the transition time is 5 ns, the turning off rate of the comparator switches is about lO ( V>'s). This can cause high amount of error voltage quantities which can not be tolerated in the comparator. So, the minimization of the switch induced error voltage is one of the important problems. The derivation of the analytical expression which models the swi tching-of f behavior of the NMOS switch, is given. Using this expression, the curves showing the dependence of the error voltage on gate voltage falling rate, transisor size and signal voltage level, have been obtained. The derivation of the same formula for PMOS and CMOS switches has been performed. It is concluded that if the sizes of NMOS and PMOS transistors are appropriately chosen, the error voltage caused by the NMOS switch can be canceled by the error voltage of the PMOS switch. In the sampling period, the inverter of the comparator must amplify a voltage difference of about 5 mV into digital output levels, in SO ns. In general, a long gate length of the transistors in the inverting amplifier is required to obtain a high gain, because an inverter with a short gate length has a low voltage gain caused by channel length modulation effect. On the other hand, it is necessary for the gate length to be short in order to obtain high speed operation. Therefore, it is difficult to attain 8 bit resolution for video frequencies if one uses only one stage TG connected inverter. Small signal analysis has shown that a two stage TG connected is necessary in order to obtain a 5 mV resolution at video speeds. The comparator has been designed using 3 fjm CMOS process and the Spice simulations are given. In a flash A/D converter, the reference resistor ladder is used to generate 2 reference voltage levels by linearly dividing the reference voltage. During the sampling period, the input capacitances of the comparators are charged to the input voltage potential while, during the autozeroing period, they are charged to the appropriate ladder tap voltages. The transient charging currents abstracted from the reference resistor ladder result in a non-uniform current flow through the ladder and produce a nonlinear division of the reference \n i aladder voltage. At the end of the autozeroing period, the resistor ladder tap voltages must be recovered from the transient state. To improve the speed and accuracy of the converter using a chopper type comparator, an analysis has been performed for the voltage variation at each reference terminal of the ladder resistor providing a reference voltage level. In the model used, the circuit made of the ladder resistor and the input capacitance of the comparator is treated as a distributed network. A theoritical formula is derived which analytically provides transient behavior of each reference terminal voltage due to change in the comparator. With this formula, it is found that the maximum error of the reference terminal voltage occurs when the input voltage is either O or Vref. The error decreases exponentially with reduction of ladder resistors and comparator input capacitances and with increase of time. ix
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